1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a dynamic random access memory.
2. Description of the Related Art
In the process of fabricating dynamic random access memory, every dynamic random access memory cell includes a field effect transistor and a capacitor, and the process requires a the bit lines to connect to the source/drain of the field effect transistors and an interconnect. Therefore, the processes for fabricating DRAM is more complicated than the process for fabricating other semiconductor devices, and the factors to be considered are also more numerous in the process integration.
As highly integrated devices are required, the device size is scaled down to fulfill design requirements. In other words, the result of devices requiring high integration reduces the space available for capacitor formation. On the other hand, computer software is gradually becoming huge, and more memory capacity is required. In the case where it is necessary to have a smaller size with sufficient memory capacity, the conventional method of fabricating the DRAM capacitor has to change in order to fulfil the requirements of the trend.
It is thus necessary to find a method that increases the present surface area of the storage node of the capacitor to increase its capacitance, while still reducing the size of the capacitor. The stacked-type capacitor is one kind of DRAM structure for increasing capacitance. There are two main types of stacked-type capacitors, which are classified by the relative position of the bit lines and capacitors. The one is the bit line over capacitor type, while the other is capacitor over bit line type.
FIG. 1 is schematic, cross-sectional view illustrating the structure of a bit line over capacitor (BOC) DRAM fabricated according to the prior art method. Referring to FIG. 1, field effect transistors 102 are formed on a substrate 100, and then capacitors 116 are formed by the conventional process. The storage nodes 110 connecting to source/drain 106 of the field effect transistors 102 are first formed, and then the top plates 114 are formed during capacitor formation. Certainly, before the top plates 114 are formed, the processes for forming a capacitor include a step of forming a capacitor dielectric layer 112 between the storage node 110 and the top plates 114. The bit lines 118 are formed after the capacitors 116 are formed. The bit lines 118 are connected to another source/drain 108 of the field effect transistor 102 by bit line contacts 120.
FIG. 2 is schematic, cross-sectional view illustrating the structure of a capacitor over bit line (COB) DRAM fabricated according to the prior art method. Referring to FIG. 2, field effect transistors 202 are formed on a substrate 200, and then bit lines 204 are formed that connect to source/drain 206 of the field effect transistor 202. After the bit lines 204 are formed, capacitors 210 are formed, which are connected to another source/drain 208 by the storage nodes 212.
As high-density integration circuit is required, not only the device size but also the spaces between devices and devices are scaled down. The BOC and COB processes of conventional DRAM are complicated, and require repeated photolithography and etching steps. Therefore, the process capability is limited in lithography accuracy and etching capability.
The processes for forming the above-mentioned BOC-type DRAM as shown in FIG. 1 must have a high degree of lithography accuracy between the gates 104 (word lines) of the field effect transistors 102 and the storage nodes 110, between the bit line contacts 120 and the top plate 114 of the capacitor 116, or between the two storage nodes 110. If misalignment occurs during the process, the devices will suffer bridging.
Similarly, the processes for forming the COB-type DRAM as shown in FIG. 2 also gives rise to some problems as in the above-mentioned BOC-type DRAM. For example, the processes are subjected to the challenge of lithography accuracy between the gates 218 (word lines) and the bit line contacts 220 of the bit lines 204, between the gates 218 (word lines) and the storage node 212, or the two storage nodes 212. On the other hand, the capacitance of the storage node 212 depends on the effective contact areas between the storage node 212 and the capacitor dielectric layer 214. In the conventional process, the capacitance of a capacitor is increased by increasing the thickness of the storage nodes 212. However, after the device is integrated, the spaces of the two storage nodes 212 are reduced. The aspect ratio of the spaces between the two storage nodes 212 is increased as the thickness of the storage nodes 212 is increased. The storage nodes 212 are difficult to separate from each other during the patterning of etching process.